TATA ELXSI - System Business Unit hiring

System Business Unit - Hiring Analog Circuit Design, Layout Design, Physical Design & Verification Engineers


The System Business Unit (SBU) of Tata Elxsi offers services to the semiconductor industry, in the Analog, Digital & Mixed Signal designs

Semicon Analog Mixed Signal (AMS) team provides complete design solution from specification to GDSII in the area of Circuit Design, Custom Layout Design, Physical design & Verification. We are the successful design partners with leading Semicon IP vendors and chip makers for the development
of Library development (Standard Cells, Memory Compiler, IOs), Analog IPs and SoCs. We have the expertise on Bipolar, CMOS & BiCMOS technologies, with process nodes varying from 0.25um to 22nm"

Job Code: SBU-IST-13

Designation : Project Lead / Team Lead / Design engineers
Experience : 2 - 9 years
Qualification : B.E/B.Tech/M.Tech/M.S/M.E in Electrical or Electronics Engg
Location : Malaysia/Bangalore/Delhi
Skills : Analog Circuit Design & Characterization


Job description:

Circuit Design of Analog Circuits such as OPAMPS, Data Converters (ADC/DAC)
Power Management Circuits (LDOs, DC-DC Converters), Phase Locked Loops
(PLLs)
Circuit Design & Characterization of Standard Cells
Circuit Design & Characterization of IOs
Circuit Design & Characterization of Memory compilers
Expertise in EDA tools. Spectre & H-Spice simulators, Exposure to Virtuoso
Layout Editor
Exposure to both Bipolar & CMOS technology, 130nm to 22nm
Expertise in Block Level & Full Chip level simulation / characterization
Tapeout Experience of medium to fairly large complex analog designs
Knowledge of Silicon Results analysis & back annotation with simulation
results


 Job Code: SBU-IST-14


Designation : Project Lead / Team Lead / Design engineers
Experience : 2 - 9 years
Qualification : B.E/B.Tech/M.Tech/M.S/M.E in Electrical or Electronics Engg
Location : Malaysia/Bangalore/Delhi
Skills : Layout Design (Analog Custom Layout / Library Development)

Job description:

Layout Design of Analog circuits such as Op-Amps, Regulators, ADC, DAC,
Power Management ICs ((LDOs, DC-DC Converters), PLLs
Layout Design of Standard Cells
Layout Design of IO Cells
Layout Design of Memory compiler
Exposure to both Bipolar & CMOS Technology, 130nm to 22nm
Expertise in Block Level & Full Chip Physical Design Verification (
DRC/LVS/RCX)
Expertise in EDA tools for Layout Design :Virtuoso, L-Edit, Assura , Calibre
Tapeout Experience of Medium to Large Complex Analog Designs / Libraries
Knowledge of Silicon Results Analysis & Back annotation with layout issues




Job Code: SBU-IST-15

Designation : Project Lead / Team Lead / Design engineers
Experience : 2 - 9 years
Qualification : B.E/B.Tech/M.Tech/M.S/M.E in Electrical or Electronics Engg
Location : Malaysia/Bangalore/Delhi
Skills : Physical Design (PD)



Job description:

Netlist to GDSII flow Implementation Floor Planning, Power Planning, Place & Route, Clock Tree Synthesis (CTS)
Physical Verification (DRC / LVS) using Assura, Calibre & Hercules
Post layout analysis ( IR Drop, SI, Cross talk)
Expertise in EDA tools Cadence SoC Encounter, Synopsys ICC, Magma Blast
Fusion / Talus
Tapeout experience on 130nm / 90nm / 65nm / 45nm / 32nm / 22nm Designs
Block Level / Full chip design implementation for medium to fairly large
designs
Knowledge of Silicon Results Analysis & Back annotation with layout issues
for ECO implementation


 Job Code: SBU-IST-16



Designation : Verification Engineers/ Sr Engineers
Experience : 3 - 8 years
Qualification : B.E/B.Tech/M.Tech/M.S/M.E
Location : Malaysia/Bangalore/Chennai
Skills : Verilog/VHDL Language Proficiency

At least two years of work experience in one of the Methodologies - OVM, VMM, AVM, UVM using SystemVerilog Working Experience in one of the Protocols like USB, PCIe, DDR, SATA etc. for at least an year

Desirable:

C based Verification at SoC Level
Gate Level Simulation



Job description:

To develop the next generation of IntelR Advanced Chipsets designs. You will be involved in functional validation (verification) of the designs Verification Environment development
Functional Verification and GLS Coverage AnalysisDebug


Resumes can be forwarded to janeethr@tataelxsi.co.in or rjaneeth@gmail.com

 

Regards,

Janeeth R